Researchers from company hewlett-Packard reported about new method of computer chips production, which will make possible to increase their speed eight times with the aid of the nano-technologies.
In this case it is reported that the commercialization of development must not engage long time, but the first products in which it can be used, will become the printers of production HP, and also some solutions of the sphere consumer electronics. The introduction of technology will require from producers the introduction of minimum changes in its production process.
Let us recall that in 1964 (six years after the invention of integrated circuit), in the process of preparation appearance, Gordon Moore (Moore's Gordon - one of the founders intel) assumed that the number of transistors on crystal will double every two years. After representing in the form of graph increase of performance in the memory microcircuits, it revealed the regularity: the new models of microcircuits were developed after identical periods - 18-24 months - after the appearance of their predecessors, and their capacity in this case grew each time approximately doubly. If this tendency is continued, Moore concluded, then the power of computers is exponential and will grow with the duration of relatively short time interval.
The use nanos-particle as wires, which connect transistors in chip, without the decrease of sizes transistors HP proposed, must substantially increase chip speed and decrease their energy consumption.
The realization of technology is expected in the chips of programmed logic FPGA (field-programmable gate array). HP proposes to use the structure of switches, which consists of the nanos-particle, located above the complementary metal-oxide semiconductors in accordance with the architecture, named FPNI (field programmable nanowire interconnect).
With the use FPNI all logical operations are produced in KMOP, and the transfer of signals occurs on nanostructure, located above the layer of transistors. Since in traditional FPGA 80-90% transistors they are used for the separation of signal, the use nano-conductors is capably essential to increase speed and effectiveness of chip.
The model of chip from FPNI, demonstrated by creators, uses nanos-wire by the width in all into 15 nm, connecting 45- nm KMOP, which will be technologically accessible to 2010. Further development of technology provides for bringing the thickness of nanos-wire to 4,5 nm, which will make possible during the application of 45- nm transistors to decrease the sizes FPGA almost into 25 (!) once in the comparison with utilized today FPGA, which consist completely of KMOP.